The prior art discloses various memory arrangements for storing data in an information handling system. In general, these memory arrangements include a memory controller function and a plurality of memory modules which are manufactured in the form of semiconductor chips having a predetermined number of memory cells. The chips are often referred to as RAM memory, Random Access Memory, in that each storage location is directly addressable as distinguished from other type of memory devices such as magnetic tape where a number of storage locations must be scanned before reaching the desired addressed location.
The number of addressable storage locations on a RAM chip is determined by the physical size of the chip and the size of each individual memory cell with some consideration for the area needed for various signal paths. The physical size of chips has been constrained more by de facto industry standards than by technology. Increases in storage capacity, however, have occurred quite rapidly over the years, primarily due to improved semiconductor material and manufacturing process techniques.
RAM memory chips or modules are currently being produced and marketed in three popular capacities, 64K, 256K, and 1 Meg.
Many older personal computers still in use employ RAM memory chips of 16K and 32K capacities while 2 Meg and 4 Meg capacities are available in limited supply for prototype development.
A 64K memory chip, for example, has 2 to the 16 power (2*16) addressable storage locations. Each storage location contains one memory cell and can store one binary bit. In most data processing systems, data is handled in "bytes" each of which consist of eight data bits and one parity bit. Data is transferred throughout the system serial by byte on a data bus consisting of eight data lines and one parity line.
In such a system, a memory bank would include nine chips or modules which store 64K bytes of data at 64K addressable storage locations. Any type of binary data may be stored in RAM memory, i.e., it may be an operating system program, an application program or user data.
The transfer of data to and from the memory involves first addressing a specific location and second, writing a byte of data or reading a byte of data from the addressed location at a particular clock time of the memory cycle. Therefore, in addition to address lines, a number of control lines are associated with each cell.
The address range of the computing system and, in turn, its maximum memory capacity is determined primarily by the the number of address lines that are provided in the system architecture. An address range of 0-64K requires 2*16 permutations of 16 binary bits. A 16 bit address is therefore needed and a 16 bit address bus must be provided if a 64K system memory is desired.
Increasing the address bus by one line effectively doubles the previous range or capacity of the system. As shown in the following table, for every address line added to the address bus, the available addressable location doubles.
______________________________________ Address Lines Addressable Locations (nominal) ______________________________________ 16 64K 17 128K 18 256K 19 512K 20 1 Meg 21 2 Meg 22 4 Meg 23 8 Meg 24 16 meg ______________________________________
It should be noted that memory capacity is not the same as address range. Memory capacity is generally expressed as byte capacity such as a 1 megabyte memory. Since some memory banks store two bytes or four bytes at an addressable location, the address range and memory capacity are only the same if the memory stores one byte of data.
Since a reasonable amount of increase in memory chip capacity is always anticipated by the system designer, many new systems are provided with more address lines than are necessary to support the current need. Also, since at any one time, three or four different capacity memory chips are available, the designer needs to provide some way to increase memory capacity above what might be marketed as a minimum system capacity.
Since the chips are replaceable easily, the user may purchase a system with minimal memory and add additional memory at a later time. If the system is designed so that only one type of memory chip may be added to the remaining empty memory banks, the problem of advising the system of the available memory installed is straightforward, provided the added memory is inserted in the correct memory banks. If not, a "hole" would exist in the address range which the operating system of the microprocessor cannot tolerate.
If the system is designed to accommodate memory chips of varying different capacities such as 64K, 256K and 1 Meg, then the problem of identifying what capacity modules are in each bank becomes somewhat more complicated. For example, assume the system is designed with a memory address range of 0 to 4 megabytes or 2*22 addressable storage locations that encompass four separate memory banks. The minimum memory capacity would be 64K bytes obtained by one bank of nine 64K modules. As the three empty banks are filled with modules, the system must be capable of identifying what capacity modules have been installed in what bank in order to select the correct memory bank and to gate the correct number of address lines to that bank, since a 64K module needs 16 lines, a 256K module needs 18 lines, and a 1 Meg module need 20 address lines.
In addition to selecting the correct number of lines, the position of the memory banks in the overall range must be contiguous. Thus, if all four banks had 64K modules and the first bank of 64K modules were replaced with 256K modules, the previous addressing line assignments to the other three banks would have to be altered.
The prior art has disclosed a number of memory system organizations which employ replaceable memory modules. These systems were faced with the problem of assigning memory banks to form a linear address range without any holes. In these systems, the memory address range was predetermined since the number of memory banks was set and only one memory module of one capacity was available.
Systems were subsequently developed that could detect a faulty module or memory bank and either reconfigure the remaining good modules to avoid any gaps in the address range or insert a spare module in place of the faulty module. These systems employed both manual and automatic arrangements in which the address range was divided into equal segments, each having a range corresponding to the number of address storage locations in each module or bank.
Since the address capacity of all range segments and modules were the same and pre-established, the reconfiguration process was relatively straightforward and simple to implement, either on a manual basis or an automatic basis. The U.S. Pat. No. 3,803,560 is a typical example of a memory system employing an automatic reconfiguration process for memory modules of the same capacity when one of those modules failed.
A memory system which employs modules of different sizes is disclosed in U.S. Pat. No. 3,813,652. The address transformation system translates an input address into a set of memory module select signals and a set of address signals. The individual modules which may have different capacities supply size type signals to hardware type adders which produce sets of composite size signals. These composite size signals are processed mathematically by hardware comparators supplied with the high order address signals in true and complimented form and by subtracters to develop a transformed address. The system requires serial processing of signals which increases processing time as the number of modules is increased in addition to requiring a relatively large number of complex circuit structures.
Systems have been developed which permit replacement of the original modules with different capacity modules, but these systems require the user to reset several switches, which basically sets the address range assigned to each memory bank. This provides greater flexibility in the use of memory modules, but is subject to error. Some systems employ a program to effectively set switches which may be more convenient, but is also subject to introduction of the wrong information and, as module sizes change, requires reprogramming.
U.S. re-issue Pat. No. 31,318 does disclose a memory system which can accommodate memory modules of different sizes and can automatically adjust the assignment of these modules to provide a linear address range when a module is replaced with a module of a different capacity. In that system each module has a signal source which indicates the capacity of the module. A hardware adder is also associated with each memory module. One input to the adder is from the capacity of the memory module. The other input to the adder is from the output of the adder of the previous memory module. The output of the adder of the instant module is feed to one input of the adder of the succeeding memory module. The output of each adder represents the cumulative capacity of all modules up to that point in the sequence. Each module has a range detector which sets the address range for the module from the input of the previous module and the output of the adder. The range detector employs two hardware comparators. One comparator determines if the input address is above the beginning address of the module and the second comparator determines if the input address is below the ending address of the module. If the comparators are true, the module is selected.
While the above system operates satisfactorily, the nature of the mathematical operations, and the comparison of the input address by the range detectors requires a relatively long memory cycle in order for signals to propagate through the comparator logic and indicate a selection of the correct memory bank. In addition, the adder circuits require additional pins on the memory modules and the high order bit processing becomes quite complex.
The present invention provides a memory system which employs a plurality of different capacity modules which are assigned to the correct segment of the system address range automatically, and if a memory module is taken out of the system and not replaced or replaced with a module of different capacity, the memory modules are automatically re-assigned to maintain a contiguous address space for the system.